The distinguishing feature of a synchronous digital system is that it has at least one system clock signal (SCS), which of course is also a digital (binary) signal. There may be other clock signals as well but all will have to be "synchronized" to the SCS which means that all other clock signals must have a known relationship in time to the SCS. Now we will consider simple systems which use only one clock signal, the SCS itself.

We have looked at how flip-flops are constructed and what makes them work. Now, we will ignore their internal characteristics and concentrate on their external (functional) behaviour. Again, the important thing to remember is that it is the clock signal which makes them work.

If we separate out the combinational elements of a general synchronous circuit and use only D-type Flip-Flops for all its sequential elements, we can define a generic sequential system by the following block diagram:

As shown above, all flip-flops change at the same time according to the Clock. Thus, we can look at the "state" of the system during two clock pulses when all flip-flop output signals are stable by looking at the outputs of the flip-flops. We have a definition now for the state of a synchronous finite-state machine, which is another name for a synchronous digital system:

and

Since after an active clock pulse occured the output of each flip-flop becomes equal to its input before the clock pulse, we can also express the first equation above as:

Since the collection of flip-flop outputs is defined as the state of the system, the last equation is called the state transition equation. The state transition equation completely describes the behaviour of the system for all times if the state of the system is known at an initial time and the inputs are known for both initial and all later times. The output of the system is a direct (combinational) function of its state and does not influence the behaviour of the system.

The advantage of the state transition description is that it has a convenient graphical representation: the state transition diagram. Let us use the example of a J-K Flip-Flop:

The functional behaviour of the J-K flip-flop is shown in the following table:

The State transition diagram is shown below:

There are (as shown), two output variables (Q, Q'); however, there is only one state variable (Q), which in this case is also equal to one of the outputs. Since there in one state variable, there are two states which we can label as State 1 and State 2, but more conveniently can be labeled by the value of Q; i.e. binary 0 or binary 1. The labels of the two states appear in the two circles.

The arrows represent the state transitions and for two inputs (JK) there should be four different combinations of the input values for each state. In this case, each transition occurs for two such input combinations. For example, if the flip-flop is in the 0 state, either the inputs JK = 00 (leave the output unchanged) or JK = 01 (reset the output) will leave the output state in state 0. Similarly, either input combination 10 (set the output to 1) or 11 (toggle the output) will change the output to become logic 1.

The simplest synchronous digital system is the binary counter because it has no input and no combinational output block. At each clock signal the counter takes up a new state and thus goes through a specific count sequence. We shall design now a binary up-counter with two outputs which goes through the sequence: 00 -> 01 -> 10 -> 11 -> 00 -> etc. The block diagram, structure and state transition diagram of a two-bit binary counter (built with two D-type flip-flops) is shown below:

From the transition table the two K-maps are constructed and the minimised Boolean expressions are shown below:

where <+> is the XOR operator.

We are given the following description of a synchronous sequential circuit to design:

A three-bit binary counter has one control input, C1. When C1=0 the counter counts up even numbers, i.e. 000 -> 010 -> 100 -> 110 -> 000 ->.... When C1=1 the counter counts down odd numbers; ie. 000 -> 111 -> 101-> 011-> 001-> 000 -> ... It is not important what sequence is produced if at the start the counter is in an undefined state (say, C1=1 and the counter output is 010), however, the counter should reach the 000 state sooner or later if enough number of clock pulses are applied.

The transition table is produced. The don't care outputs X indicate that the state is not part of the counting defined sequence:

C1 Q1 Q2 Q3 D1 D2 D3

The K-maps and the suggested minimization is indicated

We now enter the true values of the outputs into the K-map instead of the "don't care" indicators. We can do this now since the indicated minimization assigns each X to either a 0 or to a 1.

We now produce the correct transition table without don't cares (and the transition diagram if we like). As shown below, we also indicate the state transitions by State Numbers (0 to 7). After closer examination we see that the the required specifications are satisfied because for either control input case the counter will eventually reach State 0.

Build the circuit. Here we will assume that any basic gate (AND, OR, NAND, NOR, XOR, XNOR, Inverter) can be used. From the K-maps we have: