Thinking about the state diagram, we can proceed in two ways. First, we can design the computer for "variable instruction execution times", or "fixed instruction execution times". For example, three one-address instructions (INC, DEC, COMP) execute in three time steps, four in two (all the SHIFT instructions), and two (CLEAR, RETN) only in one time step. I think, we need no further complications! The simplest way to handle the problem of instructions with different number of clock cycles is to allow all instructions to execute in three time steps. While some instructions will do nothing for one or two time steps nobody will notice if we don't tell. The only complication is that the memory reference instructions may require two or four additional time steps but we cannot simplify this one; so we incorporate it into our state diagram as follows:

I sneaked in an IDLE state (they always come handy) and, unfortunately, ended up with eleven states (four flip-flops). Since the states don't always follow each other, I will need some control inputs as well. How many input lines do I need?

We must count the different possibilities. First, the processor is stuck in the IDLE state, which, I know by now, is necessary for synchronisation of the computer's operation. After that there are three cases:

Since there are four possibilities, we need two input lines, say C1 and C2. There are eleven states which requires a minimum of four flip-flops and we have two input lines -- it seems like a six-variable Karnaugh Map!! Well, I am lucky again. I know a chap down in the Special Hardware Design Department who is a wizz at designing finite state machines, he will enjoy this challenge. All I have to do is to encode the input conditions and give him the order. In three days I will have the circuit and it will be reliable and cheap. This is the note I sent him

Tony will understand what I want to do with the eleven output lines since he had designed controllers for many processors in the past. The most useful information I need later is the knowledge which state I am in at any particular time step. For the controller I asked for, during each time step (between two clock pulses) the state is indicated by one of these lines going high; all other ones being zero. This is very similar to a decoder output; but I leave the details up to Tony, he knows what he is doing.

We proceed now to encode the actual bits into the instructions. There may be some free choices, I will follow my hunch what will work out well, without bothering about too much explaining - we will see at the end whether I was right. It is important to keep the bit assignments tidy and organised because that will give me less headache later. Each class of instructions will be given specific bit patterns (I will not worry about the actual 1s and 0s), and will assign them them in numerical order. The instruction classes will be processed in decreasing order of the number of bits they need to fully encode all the instructions.

The largest number of encoded bits are required for the Two-address instructions. There are eight different instructions (3 bits) and two register designators (2 x 2 = 4 bits). Thus, seven bits are needed and we have only one bit left to indicate that this is a Two-address instruction. We use the most significant bit for this "instruction class" designator:

You may have noticed that I matched the ALU Function generator codes so that I can simply connect (if possible) the ALU function selection bits to the Instruction register bits I6-I4. However, I was not certain about the MOVE and ADDC = Add-With-Carry selections first, but noticed that the Add-with-Carry is just like an add instruction so I made its code (111) more similar to the Add code (011). Whether this will help or not, I do not know yet.

The Memory-reference instructions also need a large number of bits. There are four instructions (2 bits), one register designator (2 bits) and three different types of addressing: Immediate, Indirect, and Indirect-Indirect, which need an addressing mode indicator (2 bits); thus, a total of six bits. The three different modes and four instructions are in effect are 3 x 4 = 12 instructions. We need a minimum of four bits to encode Op-code and mode, however, we will use two bits for the type of instructions and two for the modes, which is the organised way of handling the design (nice and tidy).

We find that there are sixteen unassigned instructions here which may be used later for expansion of the instruction set. This is not a bad idea.

There are two types of One-address instruction. There are four ALU types and four SHIFTs. I will encode these separately, even though they both need the same number of bits; i.e.: two bits for the op-code and two bits for the register designator:

. .

At this stage of design the actual assignment of 0s and 1s are arbitrary. The placement of the codes are fixed. Let's not forget the subroutine RETURN instruction. I just use the next available code:

We have another three unused codes: 111001xx, 111010xx, and 111011xx, each with four possibilities. In a way, this is inefficient because not all the codes are assigned to create useful instructions. However, a bit of slack in the system is a safe way to design. We may have overlooked something and will need to patch it up later, one never knows. So far the total number of unused codes is 16+12 = 28.

Only the skip instructions remain to be encoded. I actually have four bits left to play with:

Piotr asked for as many skip instructions as possible and I can give him sixteen. On the other hand, he specified only four why should I produce more? Well, a good compromise is eight, using three bits for the conditions. I have seen a clever way (I don't remember where) to handle condition bits. Each bit in the instruction enables a condition and the total condition is true if the logical OR of the enabled conditions are true. In addition, there is one bit which reverses the total condition. In this case there are two bits which Piotr wanted to test: the Carry-Bit (CY), and the most significant bit of the A register, or A7 which indicates a negative number. The encoded conditional SKIP instructions are:

Again, there are unused instructions; i.e. the codes 11111xxx and there are eight of them. Thus, we have 36 unused instructions and will satisfy the software department's requirements without assigning them, I like it, it seems to me to be a safe design.

Wow! We have now completed a big chunk of the design (not holiday time yet!). Well, at least we have finished the encoding of the eight bits of all possible instructions. The sales department counts the number of instructions as follows: eight two-address, nine one-address, 12 memory-reference (4x3 modes), four skip instructions, a total of 33 assigned and 27 unassigned (useful for expansion) instructions (not bad for an eight-bit machine).

Now that we know what the bits mean in the instruction word, we can start hardware design in earnest. However, a review of what we have done so far will help us to proceed. First of all, the assignments of signals:

Notice that the register transfer operations MBR<--MEM is a Memory-Read, while the operation MEM<--A is a Memory-Write operation. For the first two Execute time steps E.1 and E.2 all memory reference instructions execute the same register transfer operations (this will simplify hardware -- it always does!). Also, the indirect steps are the same, regardless of instruction type.

We have twelve clock signals (i.e., there are eleven separate registers plus the memory write clock). We have already shown in Lectures 14/15 that special clock pulses are generated by the logical AND of a clock control signal and the System-Clock. Now we proceed to design the clock control signals CK1 to CK12.

A clock control signal has to be Logic-1 when a register transfer must take place. The exact time for a specific register transfer depends on the "Current State" (IDLE to I.4), of the controller and the type of instruction we are executing. In the case of the conditional skip instructions, the value of the A7 and Carry bits also play important roles.

The summarised tables shown above will help us to determine these control signals. Once we start our design, it will become clear that in addition to the specific type of the instruction (MOVE, ADD, etc), signals which indicate the Instruction-Class (whether Two-address, Shift, ... etc) will be extremely helpful. Therefore, first we design a combinational circuit which gives us these signal outputs:

We have our 1s and 0s encoded into the instruction in the Instruction-Register which specify the class of the instructions we stored there and we are expert combinational circuit designers, so I will not waste your time showing this circuit in detail. I am certain, you can design it yourself.

Even though the class of instructions require similar clock signals, some time, there are special instructions which require special handling. In a similar manner we add to the circuit above special outputs which indicate a specific instructions type. We will indicate these signals by the name of the machine instruction (MOVE, STORE, etc...).

We will use here the same general register transfer model that we used in previous lectures. We use a decoder with an enable, and a selector which determines which clock signal is generated. The clock used for enabling the decoder is the collection of all states which require updating any one of the registers. After scanning all the instructions we see that the registers are always updated in State E.3, but not for the following instructions: CMPR, RETN, SKIP, STORE, JUMP and CALL. There is a special case, the CALL instruction for which the register is updated in the E.2 state. The control signal which updates any one register is called now CREG and it can be expressed by the Boolean expression:

which requires a two-input OR gate and two AND gates, one with two, the other with seven inputs. The final circuit is then:

Sadly, we had to add two more selection lines to our design. The assignment of these new selection lines will be handled with the other ones after the design of the clock control signals.

By scanning the instructions we can see that the A register is updated in the E.1 state for all except Memory-Reference, the RETN and SKIP instructions. It is also updated for Memory-Reference instructions in state E.2. Finally, in state E.3 it is updated only for the CMPR instruction. We do not need a Karnaugh Map to write down the Boolean expression for this control signal. It is:

CK5 = E1•MEM'•RETN'•SKIP' + E.2•MEM' + E.3•CMPR

The B register is not used very much. It is used for Two-address and One-address instructions. It is only updated in state E.2. It is not used for all instructions becuase its contents are not needed; therefore, we can update it without doing any harm. Thus the simplest is to assign it as:

CK6 = E.2

which does not require circuitry at all.

The traditional rule for the Carry-bit register is that it is updated whenever the A register is updated. Thus:

CK7 = CK5

This was easy.

The PC is updated often. It is updated for all instructions in the F.2 or second Fetch state, also for all Memory-reference and the RETN and SKIP instructions in the E.1 state, for SKIP in the E.2 and finally for JUMP and CALL in the E.3 state. From these observations we have the Boolean expression:

CK8 = F.2 + E.1•(MEM + RETN + SKIP) + E.2•SKIP + E.3•(JUMP + CALL)

Actually, this expression is not completely correct. The signal SKIP indicates the class of skip instructions; however, the updating of the PC occurs only if the skip condition is satisfied. We can generate this skip condition by the CY and the A7 bits and the instruction encoded bits r (IR2), n (IR1), and c (IR0):

SKPCOND = SKIP•[ IR2 (XOR) ( IR1•A7 + IR0•CY ) ]

where the (XOR) function was used for inverting the condition when the IR2 bit value is equal to Logic-1. Using this signal then we have the correct expression for C8:

CK8 = F.2 + E.1•(MEM+RETN+SKPCOND) + E.2•SKPCOND + E.3•(JUMP+CALL)

Similar observations for MBR gives us:

CK9 = F.2 + E.2•MEM + I.2 + I.4

The instruction register is updated only in state F.3:

CK10 = F.3

Scanning the Summary tables we get:

CK11 = F.1 + E.1•MEM + I.1 + I.3

Whenever the term MEM appears at the left hand side of a register transfer operation, this clock control signal must be Logic-1. In our computer this happens only once:

CK12 = E.3 + STORE Phew.........